RFR: 8294087: RISC-V: RVC: Fix a potential alignment issue and add more alignment assertions for the patchable calls/nops [v4]

[Aleksey Shipilev]

On Wed, 21 Sep 2022 11:00:07 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

>> With RVC turning on, we must carefully keep all runtime-patchable instructions aligned. Code is running at full speed, when patching unaligned instructions spanning cache lines, concurrency issues may occur. This patch fixes a potential alignment issue of the patchable nop after MachUEPNode, with adding some strong alignment assertions as well. (In fact, currently the `nop` in the Verified Entry Point is fortunately aligned to 4 under RVC even without this patch, so this patch doesn't change program behaviors.)
>> 
>> Tested hotspot tier1 and tier2 together with other patches on QEMU.
>
> Xiaolin Zheng has updated the pull request incrementally with two additional commits since the last revision:
> 
>  - Modifications as review comments again
>  - Revert "(Revertible) Just to see which code style is better"
>    
>    This reverts commit 229d535e93ceeff4f6ba32a2c882599e2999999b.

src/hotspot/cpu/riscv/nativeInst_riscv.cpp line 274:

> 272: 
> 273:   // Must be 4 byte aligned
> 274:   MacroAssembler::assert_alignment(verified_entry);

So, if the intent to pass explicit `NativeInsn::insn_size` everywhere we say "Must be 4 bytes aligned", then we should probably pass it here too. Or, drop the explicit `NativeInsn::insn_size` everywhere else?

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PR: https://git.openjdk.org/jdk/pull/10370