RFR: 8291550: RISC-V: jdk uses misaligned memory access when AvoidUnalignedAccess enabled

[Feilong Jiang]

On Tue, 25 Apr 2023 15:37:30 GMT, Vladimir Kempik <vkempik at openjdk.org> wrote:

> Please review this attempt to remove misaligned loads and stores in risc-v specific part of jdk.
> 
> The patch has two main parts:
>  - opcodes loads/stores is now using put_native_uX/get_native_uX
>  - some code in template interp got changed to prevent misaligned loads
>  
> perf stat numbers for trp_lam ( misaligned loads) and trp_sam ( misaligned stores) before the patch: 
> 
>  169598      trp_lam                                          
>   13562      trp_sam  
> 
> 
> after the patch both numbers are zeroes.
> I can see template interpreter to be ~40 % faster on hifive unmatched ( 1 repetition of renaissance philosophers in -Xint mode), and the same performance ( before and after the patch) on thead rvb-ice ( which supports misaligned stores/loads in hw)
> 
> tier testing on hw is in progress

src/hotspot/cpu/riscv/interp_masm_riscv.cpp line 219:

> 217:     if (AvoidUnalignedAccesses)
> 218:     {
> 219:       assert(index != tmp, "must use different register");

Suggestion:

      assert_different_registers(index, tmp);

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/13645#discussion_r1177244493