RFR: 8291550: RISC-V: jdk uses misaligned memory access when AvoidUnalignedAccess enabled [v4]

[Fei Yang]

On Fri, 28 Apr 2023 09:58:53 GMT, Vladimir Kempik <vkempik at openjdk.org> wrote:

>> Please review this attempt to remove misaligned loads and stores in risc-v specific part of jdk.
>> 
>> The patch has two main parts:
>>  - opcodes loads/stores is now using put_native_uX/get_native_uX
>>  - some code in template interp got changed to prevent misaligned loads
>>  
>> perf stat numbers for trp_lam ( misaligned loads) and trp_sam ( misaligned stores) before the patch: 
>> 
>>  169598      trp_lam                                          
>>   13562      trp_sam  
>> 
>> 
>> after the patch both numbers are zeroes.
>> I can see template interpreter to be ~40 % faster on hifive unmatched ( 1 repetition of renaissance philosophers in -Xint mode), and the same performance ( before and after the patch) on thead rvb-ice ( which supports misaligned stores/loads in hw)
>> 
>> tier testing on hw is in progress
>
> Vladimir Kempik has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Remove unused macros

Changes requested by fyang (Reviewer).

src/hotspot/cpu/riscv/templateTable_riscv.cpp line 2034:

> 2032:     } else {
> 2033:       __ ld(temp, Address(temp, 0));
> 2034:     }

This if-else could be further simplified into a single "__ lwu(temp, Address(temp, 0));" since only the low 32 bits of 'temp' register is used by following 'revb_w_w'.

src/hotspot/cpu/riscv/templateTable_riscv.cpp line 2065:

> 2063:   } else {
> 2064:     __ ld(temp, Address(temp, 0));
> 2065:   }

Similar here. This if-else could be further simplified into a single "__ lwu(temp, Address(temp, 0));" too.

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PR Review: https://git.openjdk.org/jdk/pull/13645#pullrequestreview-1406968620
PR Review Comment: https://git.openjdk.org/jdk/pull/13645#discussion_r1181053857
PR Review Comment: https://git.openjdk.org/jdk/pull/13645#discussion_r1181054534