RFR: 8313779: RISC-V: use andn / orn in the MD5 instrinsic [v2]

[Antonios Printezis]

On Fri, 4 Aug 2023 14:29:19 GMT, Ludovic Henry <luhenry at openjdk.org> wrote:

>> Antonios Printezis has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   changes based on code review feedback
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 1658:
> 
>> 1656: 
>> 1657: // Rd = Rs1 & (~Rd2)
>> 1658: void MacroAssembler::andnr(Register Rd, Register Rs1, Register Rs2) {
> 
> Keep the name `andn` here, and at https://github.com/openjdk/jdk/pull/15156/files#diff-7a5c3ed05b6f3f06ed1c59f5fc2a14ec566a6a5bd1d09606115767daa99115bdR1660 use `Assembler::andn`.

Thanks. See updated patch.

> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 1671:
> 
>> 1669: void MacroAssembler::ornr(Register Rd, Register Rs1, Register Rs2) {
>> 1670:   if (UseZbb) {
>> 1671:     orn(Rd, Rs1, Rs2);
> 
> Same as above.

Ditto.

> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 4033:
> 
>> 4031:               Register rtmp1, Register rtmp2, Register rmask32) {
>> 4032:     // rtmp1 = c ^ (b | (~d))
>> 4033:     __ ornr(rtmp2, b, d);
> 
> Nit: You could use `rtmp1` here, the dependency for the next instruction will block the CPU from executing OOO anyway.

Done.

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/15156#discussion_r1284543374
PR Review Comment: https://git.openjdk.org/jdk/pull/15156#discussion_r1284543452
PR Review Comment: https://git.openjdk.org/jdk/pull/15156#discussion_r1284543541