RFR: 8318217: RISC-V: C2 VectorizedHashCode [v7]

[Yuri Gaevsky]

On Thu, 30 Nov 2023 11:32:23 GMT, Hamlin Li <mli at openjdk.org> wrote:

>> Yuri Gaevsky has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Use concrete registers for input parameters.
>
> src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp line 1479:
> 
>> 1477:   case T_SHORT:   BLOCK_COMMENT("arrays_hashcode(short) {");         break;
>> 1478:   case T_INT:     BLOCK_COMMENT("arrays_hashcode(int) {");           break;
>> 1479:   default:        BLOCK_COMMENT("arrays_hashcode {");                break;
> 
> Is this `BLOCK_COMMENT("arrays_hashcode {");                break;` necessary?

I have just borrrowed that part of code from X86 counterpart:
  https://github.com/openjdk/jdk/blob/master/src/hotspot/cpu/x86/c2_MacroAssembler_x86.cpp#L3354
It is a dead code so 'ShouldNotReachHere();' looks more appropriate here. Do you think we should fix this as a part of this patch or as some follow-ups for both x86/RISC-V?

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PR Review Comment: https://git.openjdk.org/jdk/pull/16629#discussion_r1411732405