RFR: 8315856: RISC-V: Use Zacas extension for cmpxchg [v3]

[Fei Yang]

On Mon, 11 Dec 2023 13:55:39 GMT, Andrew Haley <aph at openjdk.org> wrote:

>> Good! Yea, we discussed that internally and I thought we fixed that, those changes seems to have been lost, thanks!
>
> That `dmb` is not present in the AArch64 port because we want a release when the CAS fails, because if it fails nothing was stored, so there is literally nothing for a subsequent load from that address to synchronize with.
> 
> It's there because of this re-ordering:
> 
> 
> 
> 	<Access [A]>
> 
> 	// atomic_op (B)
> 1:	ldaxr	x0, [B]		// Exclusive load with acquire
> 	<op(B)>
> 	stlxr	w1, x0, [B]	// Exclusive store with release
> 	cbnz	w1, 1b
> 
> 	<Access [C]>
> 
> It doesn't forbid orderings such as
> 
> Load [B] -> Load [C] -> Store [A] -> Store [B]
> 
> 
> [See here](https://mail.openjdk.org/pipermail/aarch64-port-dev/2014-February/000706.html)
> 
> The Arm memory model has been strengthened, and this reasoning looks a bit shaky today. At the time we did not know if any of the usages of `cmpxchgptr`required "full barrier" semantics, so we put a full barrier in for safety's sake.

Wow, thanks for finding that history. It's very helpful for us to understand the existence of this barrier.

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PR Review Comment: https://git.openjdk.org/jdk/pull/16910#discussion_r1423296081