RFR: 8320397: RISC-V: Avoid passing t0 as temp register to MacroAssembler:: cmpxchg_obj_header/cmpxchgptr [v2]

[Robbin Ehn]

On Thu, 14 Dec 2023 08:02:39 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

>>> I don't _think_ that matters, as masm may use t1 so this 'may' kill cr. But since cr never contains any actual information and is never read (as cr), it's unclear to me, if we ever can get unwanted side-effect if either missing a "KILL cr" or have one to many, you know?
>>> 
>>> As we have fused cmp+branch I would think the graph would be better of believing we always have a live CR. We don't need to re-do the cmp to get back the killed cr, we can pretend it is still alive, since the fused branch will act as it is alive, no?
>> 
>> The C2 JIT compiler does expect something in a CR register. Check the nodes in file riscv.ad like `cmpFastLock`, `cmpFastUnlock` and `partialSubtypeCheckVsZero` [1]. That's way we emulated the CR register on riscv using the `t1` general-purpose register. I don't see another way without changing the C2's assumption about CR. 
>> 
>> [1] https://github.com/openjdk/jdk/blob/master/src/hotspot/cpu/riscv/riscv.ad#L10434
>
> Sorry, I'm not saying we should remove cr, I'm just saying I don't think need to KILL cr.
> C2 will think cr is valid all the time.

I tested removing all "KILL cr" from all riscv ad files. Compiler tests c2/codegen works fine (not 100% done yet).

Which was my theory, as we never consume or produce values in 'cr' we can see cr as always having correct values, which is nothing.

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PR Review Comment: https://git.openjdk.org/jdk/pull/16880#discussion_r1426390300