RFR: 8319716: RISC-V: Add SHA-2 [v4]

[Fei Yang]

On Fri, 15 Dec 2023 11:11:59 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

>> Robbin Ehn has updated the pull request with a new target base due to a merge or a rebase. The incremental webrev excludes the unrelated changes brought in by the merge/rebase. The pull request contains seven additional commits since the last revision:
>> 
>>  - Merge branch 'master' into sha256
>>  - Materialize constants address once
>>  - Removed template
>>  - Flag fixes
>>  - Merge branch 'master' into sha256
>>  - Share code
>>  - SHA-2
>
> Hi all, I have address all comments.
> 
> The only code change I didn't do was register caching of constants.
> This is because I don't have access to sha2 in performance simulator.
> Without it 256 and 512 have 'identical' path.
> I'll create a jira for that, so I can revisit it once I have access.
> I hope that is okay @RealFYang ? (i.e. ship this and do a follow-up)
> 
> Also @VladimirKempik the flag issue is not resolved.
> For now we use this experimental flag which is inline with the other flags.
> 
> Any other things to address, new or that I missed?
> 
> (passes compiler/intrinsics/sha/)
> 
> REF: https://bugs.openjdk.org/browse/JDK-8322177

@robehn : Thanks for the update. I am OK to leave aside caching of constants for some while when we can compare the numbers. 
I think I can take another look early next week. But I doubt about the need of saving & restoring of `t2` in the latest version.
According to the ABI, `t2` is a caller-save register and is supposed to be saved by the call is it is alive. Also, the vector registers used in this stub are also caller-save registers, we don't save them either on stub entry. 

(BTW: Seems this file should not be there in this PR: src/hotspot/cpu/riscv/.macroAssembler_riscv.cpp.swp)

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PR Comment: https://git.openjdk.org/jdk/pull/16562#issuecomment-1857925864