RFR: 8320069: RISC-V: Add Zcb instructions

[Vladimir Kempik]

On Fri, 15 Dec 2023 13:50:14 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

> Hi, this is the instructions for zcb.
> 
> Due to over lack of infrastructure having multiple extension dependent instruction does not fit well.
> Some of these compressed instructions are also missing 1 to 1 mapping, e.g. now we have a compressed not, but the corresponding instruction in uncompressed is still xor.
> I think we need to do some rework here.
> 
> I also I don't like the macro expansion as it hopeless in debugger and 'IDE's (vim+rtags for me).
> (macro stuff was originally done when templates where blacklisted in hotspot)
> 
> And I don't want an option for this, as zcb is coming in hwprobe, if you have compressed on you get them if they are supported (may depend on e.g. zbb).
> 
> I have done some modification since it passed tier1, so I'm running stuff over the weekend.

We already have "macroses" for load and stores in macroAssembler_riscv.hpp, what's the reason to do compression decision in assembler_riscv.hpp instead ( not saying it's wrong) ? https://github.com/openjdk/jdk/blob/38d94725a1a85156e30b72b325886b0e25d4db03/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp#L880

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PR Comment: https://git.openjdk.org/jdk/pull/17122#issuecomment-1860765932