RFR: 8319716: RISC-V: Add SHA-2 [v8]

[Hamlin Li]

On Thu, 21 Dec 2023 20:13:15 GMT, Hamlin Li <mli at openjdk.org> wrote:

>> Robbin Ehn has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   index store state back
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 3935:
> 
>> 3933:       // x0 is not written, we known the number of vector elements.
>> 3934: 
>> 3935:       __ vsetivli(x0, 4, vset_sew, Assembler::m1, Assembler::ma, Assembler::ta);
> 
> Currently, when MaxVectorSize < 16 UseRVV = false, so there are conditions when MaxVectorSize == 16 && UseRVV == true, in this case, `vsetivli` will not work as expected, and neither the following codes.
> 
> And 128 bits is the common one?

I see this is also pointed by @RealFYang

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PR Review Comment: https://git.openjdk.org/jdk/pull/16562#discussion_r1434848969