RFR: 8284196: RISC-V: Detect supported ISA extensions over cpuinfo [v2]

[Fei Yang]

On Tue, 7 Feb 2023 03:07:16 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> Currently, `elf_hwcap` for RISC-V only sets single-letter extension bit (e.g. IMAFD).
>> As many standard multi-letter ISA extensions are ratified (e.g. Zba/Zbb/Zbc/Zbs),
>> we should find a stable way to detect and auto-enable these supported ISA extensions
>> in JVM. [1] has proposed a way to parse supported extensions through /proc/cpuinfo
>> or "riscv,isa" string of /sys/firmware/devicetree, we could detect supported extensions
>> in the same way.
>> 
>> Here is an example of /proc/cpuinfo from Ubuntu 20.04 in QEMU-SYSTEM:
>> 
>> 
>> ubuntu at ubuntu:~$ uname -a
>> Linux ubuntu 5.8.0-14-generic #16~20.04.3-Ubuntu SMP Mon Feb 1 16:33:19 UTC 2021 riscv64 riscv64 riscv64 GNU/Linux
>> ubuntu at ubuntu:~$ cat /proc/cpuinfo 
>> processor       : 0
>> hart            : 2
>> isa             : rv64imafdch_zicsr_zifencei_zihintpause_zba_zbb_zbc_zbs_sstc
>> mmu             : sv48
>> 
>> 
>> 1: http://lists.infradead.org/pipermail/linux-riscv/2021-November/010252.html
>> 
>> 
>> Testing:
>> - [x] `jdk/bin/java -XX:+UnlockExperimentalVMOptions -XX:+UseZihintpause -XX:+UseRVV -XX:+UseZicbop -XX:+UseZba -XX:+UseZbb -XX:+UseZbs -XX:+PrintFlagsFinal -version` with release build
>
> Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:
> 
>   fix typo

Changes requested by fyang (Reviewer).

src/hotspot/os_cpu/linux_riscv/vm_version_linux_riscv.cpp line 100:

> 98:   }
> 99: }
> 100: 

Can you add a comment here about how the 'isa' substring with those extensions look like?

src/hotspot/os_cpu/linux_riscv/vm_version_linux_riscv.cpp line 102:

> 100: 
> 101: void VM_Version::get_isa() {
> 102:   char isa_buf[500];

Better to use 512 instead of 500 to be consistent with other places.

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PR: https://git.openjdk.org/jdk/pull/12343