RFR: 8284196: RISC-V: Detect supported ISA extensions over cpuinfo [v2]

[Ludovic Henry]

On Tue, 7 Feb 2023 14:17:49 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/vm_version_riscv.cpp line 186:
>> 
>>> 184:   }
>>> 185: 
>>> 186:   if (UseZba && !_cpu_features.ext_zba) {
>> 
>> We are missing where we are implicitly enabling `UseZ*` based on their corresponding values in `_cpu_feature.ext_z*`. I would assume it to be the main motivator for this change.
>
> Unlike RVC, there is still no hardware that supports those extensions. I think we should do more testing and evaluation on real hardware before enabling them by default.
> The old code may crash with sigill when users enable unsupported extensions through command line since there is no mechanism to detect multi-letter extensions. With this patch, we could complain `not supported on this CPU`  warning and continue running the program.

QEMU has good enough support to do functional testing. For performance testing, I agree it would be ideal to have proper hardware to test, but even then it's not guaranteed that a performance-minded extension would _actually_ be faster on all given hardwares. For example the original AVX-512 which led to thermal throttling.

So IMO as long as it's functional, we should want to enable it. We otherwise run the risk of "what about"-ing it until we can never enable it.

Happy to heard others' opinions as well!

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PR: https://git.openjdk.org/jdk/pull/12343