RFR: 8284196: RISC-V: Detect supported ISA extensions over cpuinfo [v2]

[Fei Yang]

On Wed, 8 Feb 2023 16:01:08 GMT, Ludovic Henry <luhenry at openjdk.org> wrote:

> > It should be safe for them to do as this PR adds the necessary detection of availability of those ISA extensions.
> 
> Ok. That also aligns RISC-V with how it's done on other platforms (SHA on x86 or AArch64 for example).
> 
> I've a slight concern with the reliability of detecting these features based solely on the device tree + being able to force enable said-features in case we know for sure the extension is available but it's not communicated by the kernel.
> 
> FYI, the kernel doesn't transfer verbatim the device-tree "isa" provided by the hardware, but it reconstruct it based on the extensions the kernel knows about. So if the hardware support a cutting edge extension (Zvknh and Zvkb for example), but the kernel is older and doesn't know about it, the hardware is going to provide a device-tree with `_Zvknh_Zvkb` to the kernel, but it's not going to show up in `/proc/cpuinfo`. (You can find the list of extensions the kernel currently knows about at [1], and the logic to build the `isa` string at [2]).

That make sense to me. My initial thought was to have some sort of checking like this PR does when users try to enable use of isa extensions on the command line. It will be better than simply crashing the JVM when their hardware are not equipped with those features. But as you mentioned, this might also bear the risk of losing the ability for them to do so. In the hope of having some stable user interface for probing riscv hardware features like [1], I guess we might need to stay with the current approach and put off this PR for some while to see. @feilongjiang : Are you OK with this?

[1] https://lkml.org/lkml/2023/2/6/1147

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PR: https://git.openjdk.org/jdk/pull/12343