RFR: 8311862: RISC-V: small improvements to slli [v2]

[Vladimir Kempik]

On Fri, 14 Jul 2023 03:18:31 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Ilya Gavrilin has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Fix typo in macroAssembler_riscv.cpp
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 4343:
> 
>> 4341:   } else {
>> 4342:     slli(Rd, Rs, shamt + 32);
>> 4343:     srli(Rd, Rd, 32);
> 
> I don't think this code in else block will work in the case when `shamt` >= 32. Note that the `slli.uw` instruction is the same as `slli` with `zext.w` performed on the least-significant word of `Rs` before shifting. So you might want to do a combination of 32-bit zero extension and `slli` on `Rs` instead.

slli.uw with shamt >= 32 will be same as ```add Rd, X0, X0```, isn't it ?
He can just add handling for that special case then

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PR Review Comment: https://git.openjdk.org/jdk/pull/14823#discussion_r1263300447