RFR: 8313322: RISC-V: implement MD5 intrinsic

[Antonios Printezis]

On Mon, 31 Jul 2023 14:53:38 GMT, Ludovic Henry <luhenry at openjdk.org> wrote:

>> What the title says. I started with the aarch64 version but changed it quite heavily.
>> 
>> I haven't done anything with the macro assembler before, so detailed / picky feedback is very welcome!
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 3954:
> 
>> 3952:   typedef RegCache<8> BufRegCache;
>> 3953: 
>> 3954:   void rotate_left_32(Register rd, Register rs, uint bits, Register rtmp1, Register rtmp2) {
> 
> That could be in `macroAssembler_riscv.hpp`

I was thinking that maybe the 32-bit version might not be as helpful in the macro assembler. But, sure. There's already `ror_imm`. Do I call it `rol32_imm`?

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PR Review Comment: https://git.openjdk.org/jdk/pull/15090#discussion_r1279494067