RFR: 8309418: RISC-V: Make use of vl1r_v & vfabs_v pseudo-instructions where appropriate

[Dingli Zhang]

Hi all,
We should add assembler functions for two pseudo-instructions vl1r_v [1] &
vfabs_v [2] and use them when appropriate for better readability.

At the same time, we removed a few unused assembly instructions.  Please take a look
and have some reviews. Thanks a lot.

[1] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#79-vector-loadstore-whole-register-instructions
[2] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#1312-vector-floating-point-sign-injection-instructions

## Testing:
qemu w/ UseRVV:
- [x] Tier1 tests (release)
- [x] Tier2 tests (release)
- [ ] Tier3 tests (release)
- [x] test/jdk/jdk/incubator/vector (release/fastdebug)

-------------

Commit messages:
 - 8309418: RISC-V: Make use of vl1r_v & vfabs_v pseudo-instructions where appropriate

Changes: https://git.openjdk.org/jdk/pull/14309/files
 Webrev: https://webrevs.openjdk.org/?repo=jdk&pr=14309&range=00
  Issue: https://bugs.openjdk.org/browse/JDK-8309418
  Stats: 19 lines in 5 files changed: 8 ins; 7 del; 4 mod
  Patch: https://git.openjdk.org/jdk/pull/14309.diff
  Fetch: git fetch https://git.openjdk.org/jdk.git pull/14309/head:pull/14309

PR: https://git.openjdk.org/jdk/pull/14309