RFR: 8309418: RISC-V: Make use of vl1r.v & vfabs.v pseudo-instructions where appropriate

[Dingli Zhang]

On Mon, 5 Jun 2023 06:51:42 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Hi all,
>> We should add assembler functions for two pseudo-instructions vl1r.v [1] &
>> vfabs.v [2] and use them when appropriate for better readability.
>> 
>> At the same time, we removed a few unused assembly instructions.  Please take a look
>> and have some reviews. Thanks a lot.
>> 
>> [1] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#79-vector-loadstore-whole-register-instructions
>> [2] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#1312-vector-floating-point-sign-injection-instructions
>> 
>> ## Testing:
>> qemu w/ UseRVV:
>> - [x] Tier1 tests (release)
>> - [x] Tier2 tests (release)
>> - [x] Tier3 tests (release)
>> - [x] test/jdk/jdk/incubator/vector (release/fastdebug)
>
> Looks good.

@RealFYang @luhenry @zifeihan Thanks for the review!

-------------

PR Comment: https://git.openjdk.org/jdk/pull/14309#issuecomment-1578040209