Integrated: 8309418: RISC-V: Make use of vl1r.v & vfabs.v pseudo-instructions where appropriate

[Dingli Zhang]

On Mon, 5 Jun 2023 06:13:08 GMT, Dingli Zhang <dzhang at openjdk.org> wrote:

> Hi all,
> We should add assembler functions for two pseudo-instructions vl1r.v [1] &
> vfabs.v [2] and use them when appropriate for better readability.
> 
> At the same time, we removed a few unused assembly instructions.  Please take a look
> and have some reviews. Thanks a lot.
> 
> [1] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#79-vector-loadstore-whole-register-instructions
> [2] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#1312-vector-floating-point-sign-injection-instructions
> 
> ## Testing:
> qemu w/ UseRVV:
> - [x] Tier1 tests (release)
> - [x] Tier2 tests (release)
> - [x] Tier3 tests (release)
> - [x] test/jdk/jdk/incubator/vector (release/fastdebug)

This pull request has now been integrated.

Changeset: 5146a582
Author:    Dingli Zhang <dzhang at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.org/jdk/commit/5146a58249bbbfdf7304e9f8062c95369ccd820f
Stats:     19 lines in 5 files changed: 8 ins; 7 del; 4 mod

8309418: RISC-V: Make use of vl1r.v & vfabs.v pseudo-instructions where appropriate

Reviewed-by: fyang, luhenry, gcao

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PR: https://git.openjdk.org/jdk/pull/14309