RFR: 8310656: RISC-V: __builtin___clear_cache can fail silently.

[Robbin Ehn]

On Thu, 29 Jun 2023 09:36:17 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Hi, please consider.
>> 
>> We recently had a bug where user were missing permissions to use this syscall.
>> Which caused crashing on, according to hs_err on things like "addi x11, x24, 0" with SIGILL.
>> If it fails it is even possible to execute valid but 'old' instruction which may not lead to a crash, instead the program misbehaves.
>> 
>> To avoid this mess I suggest that we first test the syscall during vm init and we use it directly.
>> This way we can make sure it never fails.
>> 
>> Tested failing syscall with qemu, tested t1 in qemu, t1 on jh7110 in-progress.
>
> src/hotspot/cpu/riscv/icache_riscv.cpp line 39:
> 
>> 37:   // No sush assurance is defined at the interface level of the builtin
>> 38:   // method, and so we should make sure it works.
>> 39:   __asm__ volatile("fence rw, rw" : : : "memory");
> 
> I think we should keep this inline assembly code for safe as explained by the preceding code comment.
> If I remembered correctly, such a data fence is not specified at the syscall interface level.
> 
> __asm__ volatile("fence rw, rw" : : : "memory");
> 
> Also you might want to update code comment to reflect the new code.

Yes, ok, I'll add it back and fix comment.

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PR Review Comment: https://git.openjdk.org/jdk/pull/14670#discussion_r1246682136