RFR: 8305008: RISC-V: Factor out immediate checking functions from assembler_riscv.inline.hpp [v2]

[Dingli Zhang]

On Thu, 30 Mar 2023 05:30:07 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Dingli Zhang has updated the pull request incrementally with two additional commits since the last revision:
>> 
>>  - Remove unecessary zero checking
>>  - Fix assert
>
> src/hotspot/cpu/riscv/riscv.ad line 1701:
> 
>> 1699:   if (Assembler::is_simm12(offset)) {
>> 1700:     __ addi(as_Register(reg), sp, offset);
>> 1701:   } else if (Assembler::is_simm32(offset)) {
> 
> I don't think this check is necessary since  type of 'offset' is int.

Thanks! Fixed.

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PR Review Comment: https://git.openjdk.org/jdk/pull/13202#discussion_r1152762180