RFR: 8305008: RISC-V: Factor out immediate checking functions from assembler_riscv.inline.hpp [v4]

[Fei Yang]

On Thu, 30 Mar 2023 08:08:11 GMT, Dingli Zhang <dzhang at openjdk.org> wrote:

>> The call-point to 'is_imm_in_range', 'is_unsigned_imm_in_range' and 'is_offset_in_range' in assembler_riscv.inline.hpp could to be replaced with shared code function 'is_simm' and 'is_uimm'.
>> 
>> For 'is_imm_in_range', if align_bits = 0, then the call point can be changed to call 'is_simm'. If align_bits = 1, then an additional summation judgement is added to determine if it is a multiple of 2. For 'is_unsigned_imm_in_range', we can first determine if it is greater than 0, and then call 'is_uimm' further. 'is_offset_in_range' can be changed directly to call 'is_simm'. This patch also refactored for is_valid_riscv64_address and movptr.
>> 
>> This patch removed the original functions from assembler_riscv.inline.hpp and defined some fixed-width checking functions based on the number of immediate or offset bits in the spec[1]. At the same time, we also adjusted two includes to fix the compilation error after the modification.
>> 
>> This patch also factor out 'Assembler::operand_valid_for_add_sub_immediate' and use 'is_simm12' instead.
>> 
>> Finally, this patch modified the return value in os::non_memory_address_word to avoid an imm64 value of -1 in MacroAssembler::movptr.
>> 
>> [1] https://github.com/riscv/riscv-isa-manual/releases/download/draft-20230131-c0b298a/riscv-spec.pdf
>> 
>> ### Testing:
>> 
>> On Unmatched with release build:
>> - [x] Tier1 tests
>> - [x] Tier2 tests
>> - [x] Tier3 tests
>
> Dingli Zhang has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Use is_simm12 instead

Updated changes looks good. Thanks.

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Marked as reviewed by fyang (Reviewer).

PR Review: https://git.openjdk.org/jdk/pull/13202#pullrequestreview-1364564299