RFR: 8291550: RISC-V: jdk uses misaligned memory access when AvoidUnalignedAccess enabled [v11]

[Fei Yang]

On Wed, 10 May 2023 11:42:11 GMT, Vladimir Kempik <vkempik at openjdk.org> wrote:

>> Please review this attempt to remove misaligned loads and stores in risc-v specific part of jdk.
>> 
>> The patch has two main parts:
>>  - opcodes loads/stores is now using put_native_uX/get_native_uX
>>  - some code in template interp got changed to prevent misaligned loads
>>  
>> perf stat numbers for trp_lam ( misaligned loads) and trp_sam ( misaligned stores) before the patch: 
>> 
>>  169598      trp_lam                                          
>>   13562      trp_sam  
>> 
>> 
>> after the patch both numbers are zeroes.
>> I can see template interpreter to be ~40 % faster on hifive unmatched ( 1 repetition of renaissance philosophers in -Xint mode), and the same performance ( before and after the patch) on thead rvb-ice ( which supports misaligned stores/loads in hw)
>> 
>> tier testing on hw is in progress
>
> Vladimir Kempik has updated the pull request with a new target base due to a merge or a rebase. The pull request now contains 18 commits:
> 
>  - Merge branch 'master' into LAM_SAM
>  - merge
>  - Add strig_equals patch to prevent misaligned access there
>  - rename helper function, add assertion
>  - Move misaligned lwu into macroAssembler_riscv.cpp
>  - simplify sipush and branch
>  - simpify branching in branch opcodes
>  - Remove unused macros
>  - spaces
>  - fix nits
>  - ... and 8 more: https://git.openjdk.org/jdk/compare/4aa65cbe...0c5ab1c6

src/hotspot/cpu/riscv/templateInterpreterGenerator_riscv.cpp line 1112:

> 1110:       __ lhu(t0, Address(t, 6));
> 1111:       __ slli(t0, t0, 48);
> 1112:       __ add(t1, t1, t0);

Maybe another `load_long_misaligned` assembler function for this long sequence?

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PR Review Comment: https://git.openjdk.org/jdk/pull/13645#discussion_r1190733611