RFR: 8291550: RISC-V: jdk uses misaligned memory access when AvoidUnalignedAccess enabled [v19]

[Fei Yang]

On Fri, 12 May 2023 19:13:54 GMT, Vladimir Kempik <vkempik at openjdk.org> wrote:

>> Please review this attempt to remove misaligned loads and stores in risc-v specific part of jdk.
>> 
>> The patch has two main parts:
>>  - opcodes loads/stores is now using put_native_uX/get_native_uX
>>  - some code in template interp got changed to prevent misaligned loads
>>  
>> perf stat numbers for trp_lam ( misaligned loads) and trp_sam ( misaligned stores) before the patch: 
>> 
>>  169598      trp_lam                                          
>>   13562      trp_sam  
>> 
>> 
>> after the patch both numbers are zeroes.
>> I can see template interpreter to be ~40 % faster on hifive unmatched ( 1 repetition of renaissance philosophers in -Xint mode), and the same performance ( before and after the patch) on thead rvb-ice ( which supports misaligned stores/loads in hw)
>> 
>> tier testing on hw is in progress
>
> Vladimir Kempik has updated the pull request incrementally with one additional commit since the last revision:
> 
>   resolve whitespace artifacts of github web commit

src/hotspot/cpu/riscv/templateInterpreterGenerator_riscv.cpp line 1101:

> 1099:     address unsatisfied = (SharedRuntime::native_method_throw_unsatisfied_link_error_entry());
> 1100:     __ mv(t, unsatisfied);
> 1101:     if (AvoidUnalignedAccesses) {

Flag `AvoidUnalignedAccesses` is checked in function `load_long_misaligned`. No need for another check for the same flag here. So seems that the if-else structure here could be simplified into one single line:

__ load_long_misaligned(t1, Address(t, 0), t0, 2); // 2 bytes aligned, but not 4 or 8

Looks good otherwise. Thanks again.

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PR Review Comment: https://git.openjdk.org/jdk/pull/13645#discussion_r1192911731