RFR: 8308469: [PPC64] Implement alternative fast-locking scheme

[Martin Doerr]

New alternative fast-locking scheme for PPC64. Mostly implemented like on other platforms.
Differences (also explained by comments in code):
- Not using C2HandleAnonOMOwnerStub because the C2 code is reused for native wrappers.
- Implemented a helper function `MacroAssembler::atomically_flip_locked_state` which makes it much easier to implement fast_lock/unlock for PPC64 (mainly because of register constraints in C1).
- Using acquire/release barriers only for locking/unlocking.

I have changed the C2 code to use ConditionRegister CR0 which fits better to the new locking code. Therefore, I have adapted the other modes to work with that, too.
Note that we don't support RTM with new locking modes. That feature will probably get removed in a future JDK version. (Already unsupported with Power10.)

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Commit messages:
 - Support for flag = CR0 requires small addition.
 - Make compiler_fast_lock/unlock a bit more generic and revert RTM changes.
 - 8308469: [PPC64] Implement alternative fast-locking scheme

Changes: https://git.openjdk.org/jdk/pull/14069/files
 Webrev: https://webrevs.openjdk.org/?repo=jdk&pr=14069&range=00
  Issue: https://bugs.openjdk.org/browse/JDK-8308469
  Stats: 395 lines in 7 files changed: 238 ins; 12 del; 145 mod
  Patch: https://git.openjdk.org/jdk/pull/14069.diff
  Fetch: git fetch https://git.openjdk.org/jdk.git pull/14069/head:pull/14069

PR: https://git.openjdk.org/jdk/pull/14069