RFR: 8308469: [PPC64] Implement alternative fast-locking scheme [v2]

[Martin Doerr]

On Thu, 25 May 2023 16:56:18 GMT, Martin Doerr <mdoerr at openjdk.org> wrote:

>> src/hotspot/cpu/ppc/ppc.ad line 12142:
>> 
>>> 12140: // inlined locking and unlocking
>>> 12141: 
>>> 12142: instruct cmpFastLock(flagsRegCR0 crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2) %{
>> 
>> I'm a little concerned about the usage of CR0. First it's not always clear if CR0 is altered when using the MacroAssembler, especially if not hacking ppc assembler on a daily basis. And also there might be a few instruction forms in the AD files that haven't got an effect defined for CR0 even though they alter it.
>
> There are already some nodes which use CR0 as result which is tested for quite some time. Nodes which kill it should ideally have a "kill cr0" effect, but we don't need to rely on it. C2 doesn't place other nodes between the one which sets the ConditionRegister and the conditional branch. So, using CR0 should be reliable.

It is indeed not very clear which macro assembler part kills CR0. In this case, I have made changes to support providing CR0 EQ on success and CR0 NE on failure. That is close to what other platforms do which use flags as results of lock/unlock. It is fragile, but at least, it's similar on all platforms, now.

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PR Review Comment: https://git.openjdk.org/jdk/pull/14069#discussion_r1205803751