RFR: 8308997: RISC-V: Do sign extend when comparing with zero instead of testing the sign bit

[Dingli Zhang]

RISC-V branch and jump instructions use 64-bit registers instead of 32-bit 
versions in RV64I. We use test_bit to test if bit 31 is zero to determine if a
32-bit register is less than zero currently.

However, there will be two instructions when we use test_bit to test bit
31/63 without Zbs extension[1], we can just use sign_extend instead, which
only use one instruction.

At the same time, we also change some 32-bit symbolic extension operations to
sign_extend for better readability.

[1] https://github.com/openjdk/jdk/blob/e21f865d84c7c861843ff568019e1ad11d280a50/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp#L4596-L4603

## Testing:
Unmatched:
- [x] Tier1 tests (release)
- [x] Tier2 tests (release)
- [x] Tier3 tests (release)

-------------

Commit messages:
 - 8308997: RISC-V: Do sign extend when comparing with zero instead of testing the sign bit

Changes: https://git.openjdk.org/jdk/pull/14197/files
 Webrev: https://webrevs.openjdk.org/?repo=jdk&pr=14197&range=00
  Issue: https://bugs.openjdk.org/browse/JDK-8308997
  Stats: 45 lines in 8 files changed: 0 ins; 7 del; 38 mod
  Patch: https://git.openjdk.org/jdk/pull/14197.diff
  Fetch: git fetch https://git.openjdk.org/jdk.git pull/14197/head:pull/14197

PR: https://git.openjdk.org/jdk/pull/14197