RFR: 8318218: RISC-V: C2 CompressBits [v3]

[Fei Yang]

On Wed, 8 Nov 2023 07:32:34 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Hamlin Li has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Match Op_CompressBits based on UseRVV only
>
> src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp line 1684:
> 
>> 1682: }
>> 1683: 
>> 1684: void C2_MacroAssembler::compress_bits_v(Register dst, Register src, Register mask, Register tmp, bool is_long) {
> 
> Seems that this is quite similar to the implementation of `CompressM` node in `riscv_v.ad` [1] which I think should be more efficient. The only difference is that we only need to move `src` into a vector register beforehand and change to perform `vcpop_m` under the given `mask`. Please consider.
> 
> [1] https://github.com/openjdk/jdk/blob/master/src/hotspot/cpu/riscv/riscv_v.ad#L3506-L3518

Ah, I see the difference now. The active 0 bits are still kept back here in this case [1]. 

[1] https://github.com/openjdk/jdk/blob/master/src/hotspot/share/opto/intrinsicnode.cpp#L300-L310

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PR Review Comment: https://git.openjdk.org/jdk/pull/16481#discussion_r1386157421