RFR: 8318218: RISC-V: C2 CompressBits [v6]

[Fei Yang]

On Fri, 10 Nov 2023 15:07:51 GMT, Hamlin Li <mli at openjdk.org> wrote:

> Yes, that's the potential possible issues. Or maybe we can tighten the matcher rule to enable the intrinsic: for example, `return UseRVV && (MaxVectorSize >= 32)` (or even 64) in `Matcher::match_rule_supported`, so for Long it will be v2(v3), v4(v5), for Integer, it will v2, v4, just any 2 vector regs if we tighten the match rule to >=64. Does this make sense?

I see chip vendors are shipping products with RVV VLEN of 128 bits. So I think it's more reasonable to go with the current implementation for now. While it seems that this would win in respect of number if instruction executed compared with the scalar version, we still need to revisit/bechmark this change when we have access to the real RVV hardware.

-------------

PR Comment: https://git.openjdk.org/jdk/pull/16481#issuecomment-1807557750