RFR: 8318218: RISC-V: C2 CompressBits [v6]

[Hamlin Li]

On Mon, 13 Nov 2023 06:27:18 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Hamlin Li has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   reserve all used v register; use t0 directly
>
> src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp line 1691:
> 
>> 1689: 
>> 1690:   // load the src data(in bits) to be compressed.
>> 1691:   vsetivli(x0, 1, sew, lmul);
> 
> A default `lmul` of `m1` is enough to perform the succeeding `vmv_s_x` instuction as specified by the RVV spec.
> 
> The integer scalar read/write instructions transfer a single value between a scalar x register and element 0 of a vector
> register. The instructions ignore LMUL and vector register groups.

Seems it make no difference at run time, as `The instructions ignore LMUL and vector register groups.`.
But it makes sense to modify it as you suggested, it's more clear.

> src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp line 1703:
> 
>> 1701:   // load the mask data(in bits).
>> 1702:   vsetivli(x0, 1, sew, lmul);
>> 1703:   vmv_v_x(v0, mask);
> 
> Shouldn't this be `vmv_s_x(v0, mask)` instead of `vmv_v_x(v0, mask)`? The `vcompress.vm` instruction is expecting a vector mask register. Also the preceding `vsetivli` should be changed to use a default `lmul` of `m1` at the same time.

Good catch!

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/16481#discussion_r1391031706
PR Review Comment: https://git.openjdk.org/jdk/pull/16481#discussion_r1391031969