RFR: 8318217: RISC-V: C2 VectorizedHashCode [v2]

[Hamlin Li]

On Thu, 16 Nov 2023 09:06:05 GMT, Yuri Gaevsky <duke at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/riscv.ad line 10306:
>> 
>>> 10304: 
>>> 10305: 
>>> 10306: instruct arrays_hashcode(iRegP_R11 ary, iRegI_R12 cnt, iRegI_R10 result, immI basic_type,
>> 
>> Is it necessary to specify the regs(r11/12/10) here?
>
> I've just "borrowed" those definitions from other intrinsics around. Do you think we can improve this with iRegP/iRegI?

Seems to me it's not necessary to specify the registers. Can you try it?

>> src/hotspot/cpu/riscv/riscv.ad line 10312:
>> 
>>> 10310:   match(Set result (VectorizedHashCode (Binary ary cnt) (Binary result basic_type)));
>>> 10311:   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6,
>>> 10312:          USE_KILL ary, USE_KILL cnt, USE basic_type, KILL cr);
>> 
>> should `TEMP_DEF result` be added here?
>
> Hmm, addition of TEMP_DEF result makes the bencmark results even worse tha without intrinsic (I haven't look at the generated assembler though).

What specific tests were run for this intrinsic implementation to verify the correctness?
BTW, can you add some comments about what java method or bytecode this intrinsic is for?

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PR Review Comment: https://git.openjdk.org/jdk/pull/16629#discussion_r1396077210
PR Review Comment: https://git.openjdk.org/jdk/pull/16629#discussion_r1396087016