RFR: 8318217: RISC-V: C2 VectorizedHashCode [v2]

[Yuri Gaevsky]

On Wed, 15 Nov 2023 15:52:42 GMT, Yuri Gaevsky <duke at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp line 1477:
>> 
>>> 1475:   case T_SHORT:   BLOCK_COMMENT("arrays_hashcode(short) {");         break;
>>> 1476:   case T_INT:     BLOCK_COMMENT("arrays_hashcode(int) {");           break;
>>> 1477:   default:        BLOCK_COMMENT("arrays_hashcode {");                break;
>> 
>> In `C2_MacroAssembler::arrays_hashcode_elsize`, default action is `ShouldNotReachHere();`, should it be consistent here?
>
> Sure, thanks for catching!

Done.

>> src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp line 1540:
>> 
>>> 1538:   addw(result, result, tmp1); // result = result + ary[i]
>>> 1539:   subw(cnt, cnt, 1);
>>> 1540:   add(ary, ary, elsize);
>> 
>> Similar comment for cnt and ary as chunk and ary above.
>
> As above, please advice how to do that. IIUC, that's possible with INDEX-REG addressing which is absent in RISC-V. :-(

Done.

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/16629#discussion_r1397724570
PR Review Comment: https://git.openjdk.org/jdk/pull/16629#discussion_r1397724873