RFR: 8319716: RISC-V: Add SHA-2

[Fei Yang]

On Mon, 20 Nov 2023 16:00:43 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 3769:
>> 
>>> 3767:     __ vslidedown_vi(v16, v27, 2);                   // v16 = {_,_,e,f}
>>> 3768:     // Merge elements [3..2] of v26 ({a,b}) into elements [3..2] of v16
>>> 3769:     __ vmerge_vvm(v16, v26, v16);                    // v16 = {a,b,e,f}
>> 
>> I see the openssl version makes use of index-load to get {f,e,b,a},{h,g,d,c} pre-loop and index-store to put {f,e,b,a},{h,g,d,c} back to {a,b,c,d},{e,f,g,h} post-loop, which is much simpler than this code. Please consider.
>> 
>> [1] https://github.com/openssl/openssl/blob/master/crypto/sha/asm/sha256-riscv64-zvkb-zvknha_or_zvknhb.pl#L124-L142
>
> The vsetivli is often expensive:ish,  the code in openssl sets it five times before reaching first round.
> That don't seem like a good idea, now vsetivli make the code much easier to read yes...
> 
> I guess I need to check numbers for that also.. :)

Yeah. Why not consider something more simpler if there is no known big difference on performance numbers? And this is the first version when RVV-1.0 compatible hardwares are not popular yet :-)

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PR Review Comment: https://git.openjdk.org/jdk/pull/16562#discussion_r1400183278