RFR: 8319716: RISC-V: Add SHA-2

[Fei Yang]

On Tue, 21 Nov 2023 08:59:10 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

>> __ vadd_vv(v14, v15, v11);
>>     <load can start>             <<----------------------------------------------------------|
>>     __ vsha2cl_vv(v17, v16, v14);                                                            |
>>     __ vsha2ch_vv(v16, v17, v14);                                                            |
>>     __ vmerge_vvm(v14, v13, v12);                                                            |
>>     __ vsha2ms_vv(v11, v14, v10); // Generate W[23:20]                                       |
>>     //--------------------------------------------------------------------------------       |
>>     // Quad-round 2 (+2, v12->v13->v10->v11)                                                 |
>>     __ vl1re32_v(v15, consts); ---------------------------------------------------------------
>> 
>> 
>> No ?
>
> If you consider register renaming load should be enable to start even earlier.
> E.g. load into vX, then rename vX to v15 after the add that uses v15.

Thanks. Now I see what you mean. That makes sense to me. It will be interesting to see how the performance numbers may vary. Unfortunately, I don't have access to the hardware yet.

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PR Review Comment: https://git.openjdk.org/jdk/pull/16562#discussion_r1400324480