RFR: 8319716: RISC-V: Add SHA-2 [v2]

[Robbin Ehn]

On Wed, 15 Nov 2023 07:08:04 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Robbin Ehn has updated the pull request with a new target base due to a merge or a rebase. The incremental webrev excludes the unrelated changes brought in by the merge/rebase. The pull request contains four additional commits since the last revision:
>> 
>>  - Flag fixes
>>  - Merge branch 'master' into sha256
>>  - Share code
>>  - SHA-2
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 3700:
> 
>> 3698:     Register ofs   = c_rarg2;
>> 3699:     Register limit = c_rarg3;
>> 3700:     Register consts = t0;
> 
> I would suggest choose a different temporary register for `consts`, maybe `t2`. Using x5 (t0) / x6 (t1) to keep some long-lived values like `consts` can be error prone. Those two are reserved scratch registers which could be explictly / implicitly clobberred by various assembler functions.

Fixed

> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 4215:
> 
>> 4213:     __ vslidedown_vi(v16, v27, 2);                   // v16 = {_,_,e,f}
>> 4214:     // Merge elements [3..2] of v26 ({a,b}) into elements [3..2] of v16
>> 4215:     __ vmerge_vvm(v16, v26, v16);                    // v16 = {a,b,e,f}
> 
> Simlar here. Can we make use of index-load and index-store to simplify the code for the 512 case too?

Not yet addressed.

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PR Review Comment: https://git.openjdk.org/jdk/pull/16562#discussion_r1407830224
PR Review Comment: https://git.openjdk.org/jdk/pull/16562#discussion_r1407830822