RFR: 8319716: RISC-V: Add SHA-2 [v2]

[Robbin Ehn]

On Thu, 9 Nov 2023 17:39:09 GMT, Hamlin Li <mli at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 3917:
>> 
>>> 3915:     //--------------------------------------------------------------------------------
>>> 3916:     // Quad-round 0 (+0, v10->v11->v12->v13)
>>> 3917:     __ vl1re32_v(v15, consts);
>> 
>> Seems the round 0-11 are quite similar with each other, although with some difference in some src registers, but with similar patterns.
>> Would it be possible and better to group them in a loop to simplify the code? or construct some functions.
>
> Seems also that generate_sha256_implCompress and generate_sha512_implCompress can share some code, looks like they are quite similar at a brief look.

Now they share code.

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PR Review Comment: https://git.openjdk.org/jdk/pull/16562#discussion_r1407829086