RFR: 8316180: Thread-local backoff for secondary_super_cache updates [v12]

[Aleksey Shipilev]

> See more details in the bug and related issues.
> 
> This is the attempt to mitigate [JDK-8180450](https://bugs.openjdk.org/browse/JDK-8180450), while the more complex fix that would obviate the need for `secondary_super_cache` is being worked out. The goal for this fix is to improve performance in pathological cases, while keeping non-pathological cases out of extra risk, *and* staying simple enough and reliable for backports to currently supported JDK releases.
> 
> This implements mitigation on most current architectures:
>   - ✅ x86_64: implemented
>   - 🔴 x86_32: considered, abandoned; cannot be easily done without blowing up code size
>   - ✅ AArch64: implemented
>   - 🔴 ARM32: considered, abandoned; needs cleanups and testing; see [JDK-8318414](https://bugs.openjdk.org/browse/JDK-8318414)
>   - ✅ PPC64: implemented, thanks @TheRealMDoerr 
>   - ✅ S390: implemented, thanks @offamitkumar 
>   - ✅ RISC-V: implemented, thanks @RealFYang 
>   - ✅ Zero: does not need implementation
> 
> Note that the code is supposed to be rather compact, because it is inlined in generated code. That is why, for example, we cannot easily do x86_32 version: we need a thread, so the easiest way would be to call into VM. But we cannot that easily: the code blowout would make some forward branches in external code non-short. I think we we cannot implement this mitigation on some architectures, so be it, it would be a sensible tradeoff for simplicity.
> 
> Setting backoff at `0` effectively disables the mitigation, and gives us safety hatch if something goes wrong.
> 
> I believe we can go in with `1000` as the default, given the experimental results mentioned in this PR.
> 
> Additional testing:
>  - [x] Linux x86_64 fastdebug, `tier1 tier2 tier3`
>  - [x] Linux AArch64 fastdebug, `tier1 tier2 tier3`

Aleksey Shipilev has updated the pull request incrementally with four additional commits since the last revision:

 - Editorial cleanups
 - RISC-V implementation
 - Mention ARM32 bug
 - Make sure benchmark runs with C1

-------------

Changes:
  - all: https://git.openjdk.org/jdk/pull/15718/files
  - new: https://git.openjdk.org/jdk/pull/15718/files/8dd00325..0e1fccd2

Webrevs:
 - full: https://webrevs.openjdk.org/?repo=jdk&pr=15718&range=11
 - incr: https://webrevs.openjdk.org/?repo=jdk&pr=15718&range=10-11

  Stats: 24 lines in 7 files changed: 15 ins; 3 del; 6 mod
  Patch: https://git.openjdk.org/jdk/pull/15718.diff
  Fetch: git fetch https://git.openjdk.org/jdk.git pull/15718/head:pull/15718

PR: https://git.openjdk.org/jdk/pull/15718