RFR: 8318723: RISC-V: C2 UDivL [v2]

[Hamlin Li]

On Wed, 25 Oct 2023 15:34:43 GMT, Hamlin Li <mli at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/macroAssembler_riscv.hpp line 244:
>> 
>>> 242:   // idiv variant which deals with MINLONG as dividend and -1 as divisor
>>> 243:   int corrected_idivl(Register result, Register rs1, Register rs2,
>>> 244:                       bool want_remainder, bool is_signed = true);
>> 
>> Could you not set the default value of `is_signed` to `true`, to make it clear which case it is at the callsite.
>
> The reason I use a default value for `is_signed` is because both corrected_idivx are also used in cpu/riscv/c1_LIRAssembler_arith_riscv.cpp, which I dont' want to touch in this pr.
> But if you insist, I can remove the default.

I have removed the default values.

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PR Review Comment: https://git.openjdk.org/jdk/pull/16346#discussion_r1372831046