RFR: 8318953: RISC-V: Small refactoring for MacroAssembler::test_bit [v2]

[Gui Cao]

On Fri, 27 Oct 2023 07:30:03 GMT, Gui Cao <gcao at openjdk.org> wrote:

>> Hi, The current test_bit assembly function needs to accept a temporary register because it needs one if it goes to the andi else branch. However, in this case we can actually avoid calling andi and accomplish the same thing by logically shifting to the right and testing the lowest bit. The advantage is that it makes the test_bit function much simpler. Also, to reduce the number of instructions in a given case (consider the mv function), mv actually calls the li function, which generates more than one instruction when the parameter imm exceeds the 32-bit range.
>> https://github.com/openjdk/jdk/blob/9123961aaa47aa58ec436640590d2cceedb8cbb1/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp#L2009-L2017
>> https://github.com/openjdk/jdk/blob/9123961aaa47aa58ec436640590d2cceedb8cbb1/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp#L730
>> https://github.com/openjdk/jdk/blob/9123961aaa47aa58ec436640590d2cceedb8cbb1/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp#L804-L840
>> 
>> ### Testing:
>> qemu 8.1.50:
>> - [x] Tier1 tests (fastdebug)
>> - [x] Tier2 tests (release)
>> - [x] Tier3 tests (release)
>
> Gui Cao has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Use and_imm12 to replace andi in test_bit

tier1-3 test passed.

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PR Comment: https://git.openjdk.org/jdk/pull/16391#issuecomment-1784149248