RFR: 8315841: RISC-V: Check for hardware TSO support [v4]

[Robbin Ehn]

On Thu, 7 Sep 2023 12:00:30 GMT, Ludovic Henry <luhenry at openjdk.org> wrote:

>> With the Ztso extension [1], some hardware will support TSO on RISC-V. That allows us to reduce the generation of memory fences, given the stronger memory model compared to RVWMO.
>> 
>> [1] https://github.com/riscv/riscv-isa-manual/blob/6dcbc6da9ada01f0f57da83cda6059bdec57619f/src/ztso-st-ext.adoc#L1
>
> Ludovic Henry has updated the pull request incrementally with one additional commit since the last revision:
> 
>   fixup! 8315841: RISC-V: Check for hardware TSO support

Thanks, looks good (minus a nit).

src/hotspot/cpu/riscv/macroAssembler_riscv.hpp line 381:

> 379:   void fence(uint32_t predecessor, uint32_t successor) {
> 380:     if (UseZtso) {
> 381:       if (pred_succ_to_membar_mask(predecessor, successor) & StoreLoad) {

This should be "(pred_succ_to_membar_mask(predecessor, successor) & StoreLoad) == 0".

src/hotspot/cpu/riscv/vm_version_riscv.cpp line 213:

> 211:   }
> 212: 
> 213: #if defined(TARGET_ZTSO) && TARGET_ZTSO

If someone compiles with "CXXFLAGS=-marchrv64....ztso..", we need to try to parse the supplied flags, that doesn't seem like fun.
Instead I suggest we add code to read-out the elf flags, i.e:
"Flags:                             0x15, RVC, double-float ABI, TSO"

And set UseZtso:
A: If this is a TSO elf.
B: If hwprobe says this TSO hardware (either directly or via vendor).
C: If someone set flag,

I guess your idea was to have a flag like --enable-tso which sets TARGET_TSO ?
If we have that or not I still like above to happen.

(I'm not saying you should do any of this in this PR, I can file new ones)

-------------

Marked as reviewed by rehn (Reviewer).

PR Review: https://git.openjdk.org/jdk/pull/15613#pullrequestreview-1615312026
PR Review Comment: https://git.openjdk.org/jdk/pull/15613#discussion_r1318530105
PR Review Comment: https://git.openjdk.org/jdk/pull/15613#discussion_r1318549490