RFR: 8315841: RISC-V: Check for hardware TSO support [v4]

[Robbin Ehn]

On Thu, 7 Sep 2023 12:36:54 GMT, Vladimir Kempik <vkempik at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/macroAssembler_riscv.hpp line 392:
>> 
>>> 390:     Assembler::fence(predecessor, successor);
>>> 391:   }
>>> 392: 
>> 
>> Suggestion:
>> 
>>   void fence(uint32_t predecessor, uint32_t successor) {
>>     if (UseZtso) {
>>       if (pred_succ_to_membar_mask(predecessor, successor) & StoreLoad) {
>>         // TSO allows for stores to be reordered after loads. When the compiler
>>         // generates a fence to disallow that, we are required to generate the
>>         // fence for correctness.
>>         Assembler::fence(predecessor, successor);
>>       } else {
>>         // TSO guarantees other orderings already.
>>       }
>>     }
>>   }
>
> @theRealAph this way we will miss fence completely when UseZtso is false

I prefer:

{
  if (UseZtso) {
    ....
    return;
  }
  <the other code path without else>
}

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/15613#discussion_r1318559284