RFR: 8315716: RISC-V: implement ChaCha20 intrinsic

[Hamlin Li]

On Wed, 27 Sep 2023 09:37:10 GMT, Ludovic Henry <luhenry at openjdk.org> wrote:

> Only need to do the `li` -> `mv` change and it's LGTM. Also, please change the PR title to `8315716: RISC-V: implement ChaCha20 intrinsic` to link it back to JBS. Thanks!

Thanks for reviewing!

> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 4281:
> 
>> 4279: 
>> 4280:   // rotate vector register left with shift bits, 32-bit version
>> 4281:   void rotate_left_imm(VectorRegister rv, uint32_t shift, VectorRegister tmp_vr) {
> 
> This should be in `macroAssembler_riscv.cpp` instead. I would also call it something like `vrolwi`. That'll more closely match the [`vrol`](https://github.com/riscv/riscv-crypto/blob/c8ddeb7e64a3444dda0438316af1238aeed72041/doc/vector/insns/vrol.adoc#L5)

Thanks Ludovic, Fixed.

> src/hotspot/cpu/riscv/vm_version_riscv.cpp line 255:
> 
>> 253:       FLAG_SET_DEFAULT(UseChaCha20Intrinsics, true);
>> 254:     }
>> 255:   }
> 
> You can have something like that:
> 
> Suggestion:
> 
>   if (UseRVV) {
>     if (FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
>       FLAG_SET_DEFAULT(UseChaCha20Intrinsics, true);
>     }
>   } else if (UseChaCha20Intrinsics) {
>     if (!FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
>       warning("Chacha20 Intrinsics requires RVV instructions (not available on this CPU)");
>     }
>     FLAG_SET_DEFAULT(UseChaCha20Intrinsics, false);
>   }

Thanks Ludovic!

-------------

PR Comment: https://git.openjdk.org/jdk/pull/15899#issuecomment-1737096689
PR Review Comment: https://git.openjdk.org/jdk/pull/15899#discussion_r1335923012
PR Review Comment: https://git.openjdk.org/jdk/pull/15899#discussion_r1337586626