RFR: 8315716: RISC-V: implement ChaCha20 intrinsic [v2]

[Hamlin Li]

On Thu, 28 Sep 2023 14:47:08 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

>> Hamlin Li has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   revert adding t3-t6
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 4327:
> 
>> 4325:     const Register length = t2;
>> 4326:     const Register avl = t3;
>> 4327:     const Register stride = t4;
> 
> There seems to be no overlapping with loop/t0.
> So avl van just be t0? No need for a fourth/fifth temp reg?

Thanks Robbin, I've reverted adding t3-t6.

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PR Review Comment: https://git.openjdk.org/jdk/pull/15899#discussion_r1340423091