RFR: 8315716: RISC-V: implement ChaCha20 intrinsic [v2]

[Robbin Ehn]

On Fri, 29 Sep 2023 14:50:13 GMT, Antonios Printezis <tonyp at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/assembler_riscv.hpp line 150:
>> 
>>> 148: constexpr Register t5 = x30;
>>> 149: constexpr Register t6 = x31;
>>> 150: 
>> 
>> In your case it doesn't look like we need them?
>> 
>> So I think you should revert these changes.
>> As we may want to reserve one of those registers for something in the future.
>> I don't think we should take lightly on just start using them.
>
> @robehn Not sure I understand this argument. We can still use the registers using `x[28-31]`. Why not give them their more informative name? Also, I do use them in the MD5 intrinsic, FWIW.

Yes, I see what you mean.
I think I was just wrong.

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PR Review Comment: https://git.openjdk.org/jdk/pull/15899#discussion_r1341727249