RFR: 8345236: RISC-V: Remove revb_h_h_u and revb_h_w_u macro assembler routines [v2]

[Feilong Jiang]

On Fri, 29 Nov 2024 09:56:55 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Hi, please consider this cleanup change.
>> 
>> This is a further step after https://bugs.openjdk.org/browse/JDK-8345110.
>> `revb_h_h_u` and `revb_h_w_u` assembler routines are mainly used to change byte-ordering for one halfword and two halfwords respectively. But the names don't look obvious and the callsites will emit more instructions when Zbb is not available (6 and 14 instructions respectively).
>> 
>> Since we don't have instructions like aarch64 `rev32` or `rev16`, seems more reasonable for us to do the byte-ordering while loading the bytes for these callsites, which also results in less instructions. Similar approach is taken for other places in riscv [1] and other ports like arm [2]. This also renames `revb_w` into `revbw` so that we are more consistent in naming with integer instructions that manipulate 32-bit values like `addiw`.
>> 
>> [1] https://github.com/openjdk/jdk/blob/master/src/hotspot/cpu/riscv/templateTable_riscv.cpp#L1625
>> [2] https://github.com/openjdk/jdk/blob/master/src/hotspot/cpu/arm/templateTable_arm.cpp#L756
>> 
>> Testing on linux-riscv64 platform.
>> - [x] tier1 (release)
>> - [x] non-trivial benchmark workloads like Dacapo, SpecJBB, Renaissance (release)
>
> Fei Yang has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Fix indentation

Thanks for the cleanup!

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Marked as reviewed by fjiang (Committer).

PR Review: https://git.openjdk.org/jdk/pull/22452#pullrequestreview-2471286217