RFR: 8345322: RISC-V: Add concurrent gtests for cmpxchg variants [v4]

[Fei Yang]

On Wed, 11 Dec 2024 09:26:13 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

>> Hi, please consider these additional concurrent tests.
>> 
>> (this will not go into 24)
>> 
>> There are two concurrent counter versions:
>> - Each thread is exclusively responsible for an certain increment steps
>> - Each thread plainly tries to CAS increment by one
>> 
>> I refactored the code, so these concurrent versions can reuse the generated CAS functions.
>> 
>> 
>> [ RUN      ] RiscV.cmpxchg_int64_concurrent_lr_sc_vm
>> [       OK ] RiscV.cmpxchg_int64_concurrent_lr_sc_vm (24 ms)
>> [ RUN      ] RiscV.cmpxchg_int64_concurrent_maybe_zacas_vm
>> [       OK ] RiscV.cmpxchg_int64_concurrent_maybe_zacas_vm (12 ms)
>> [ RUN      ] RiscV.cmpxchg_int32_concurrent_lr_sc_vm
>> [       OK ] RiscV.cmpxchg_int32_concurrent_lr_sc_vm (14 ms)
>> [ RUN      ] RiscV.cmpxchg_int32_concurrent_maybe_zacas_vm
>> [       OK ] RiscV.cmpxchg_int32_concurrent_maybe_zacas_vm (14 ms)
>> [ RUN      ] RiscV.cmpxchg_int16_concurrent_lr_sc_vm
>> [       OK ] RiscV.cmpxchg_int16_concurrent_lr_sc_vm (15 ms)
>> [ RUN      ] RiscV.cmpxchg_int16_concurrent_maybe_zacas_vm
>> [       OK ] RiscV.cmpxchg_int16_concurrent_maybe_zacas_vm (14 ms)
>> [ RUN      ] RiscV.cmpxchg_int8_concurrent_lr_sc_vm
>> [       OK ] RiscV.cmpxchg_int8_concurrent_lr_sc_vm (14 ms)
>> [ RUN      ] RiscV.cmpxchg_int8_concurrent_maybe_zacas_vm
>> [       OK ] RiscV.cmpxchg_int8_concurrent_maybe_zacas_vm (14 ms)
>> [ RUN      ] RiscV.weak_cmpxchg_int64_concurrent_lr_sc_vm
>> [       OK ] RiscV.weak_cmpxchg_int64_concurrent_lr_sc_vm (15 ms)
>> [ RUN      ] RiscV.weak_cmpxchg_int64_concurrent_maybe_zacas_vm
>> [       OK ] RiscV.weak_cmpxchg_int64_concurrent_maybe_zacas_vm (11 ms)
>> [ RUN      ] RiscV.weak_cmpxchg_int32_concurrent_lr_sc_vm
>> [       OK ] RiscV.weak_cmpxchg_int32_concurrent_lr_sc_vm (15 ms)
>> [ RUN      ] RiscV.weak_cmpxchg_int32_concurrent_maybe_zacas_vm
>> [       OK ] RiscV.weak_cmpxchg_int32_concurrent_maybe_zacas_vm (12 ms)
>> [ RUN      ] RiscV.weak_cmpxchg_int16_concurrent_lr_sc_vm
>> [       OK ] RiscV.weak_cmpxchg_int16_concurrent_lr_sc_vm (13 ms)
>> [ RUN      ] RiscV.weak_cmpxchg_int16_concurrent_maybe_zacas_vm
>> [       OK ] RiscV.weak_cmpxchg_int16_concurrent_maybe_zacas_vm (14 ms)
>> [ RUN      ] RiscV.weak_cmpxchg_int8_concurrent_lr_sc_vm
>> [       OK ] RiscV.weak_cmpxchg_int8_concurrent_lr_sc_vm (13 ms)
>> [ RUN      ] RiscV.weak_cmpxchg_int8_concurrent_maybe_zacas_vm
>> [       OK ] RiscV.weak_cmpxchg_int8_concurrent_maybe_zacas_vm (15 ms)
>> 
>> 
>> Execute with +UseZacas, and without on BPI-F3.
>> 
>> Thanks, Robbin
>
> Robbin Ehn has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Inclusive case

test/hotspot/gtest/riscv/test_assembler_riscv.cpp line 296:

> 294:   bool zacas = UseZacas;
> 295:   UseZacas = false;
> 296:   run_plain_cmpxchg_tests<uint32_t, Assembler::uint32>();

Not quite sure if we should cover `uint32` type here. `lr.w` used to implement the CAS operation loads a 32-bit word and sign-extend it.

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PR Review Comment: https://git.openjdk.org/jdk/pull/22574#discussion_r1879886196