RFR: 8346235: RISC-V: Optimize bitwise AND with mask values [v2]

[Fei Yang]

On Sun, 15 Dec 2024 15:03:14 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> Fei Yang has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Review comment
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 5867:
> 
>> 5865: 
>> 5866:   if (bits == 8) {
>> 5867:     andi(dst, src, 0xFF);
> 
> Maybe we could move `andi` to here:
> https://github.com/openjdk/jdk/blob/6b022bb64b2109c8cd40ebd3b8b3226cf894544d/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp#L5855-L5859

Make sense. I just find that `zext_b(dst, src);` should not depend on `UseZbb`. So I just removed this check. Thanks.

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PR Review Comment: https://git.openjdk.org/jdk/pull/22752#discussion_r1885751106