RFR: 8346475: RISC-V: Small improvement for MacroAssembler::ctzc_bit

[Fei Yang]

Hi, please review this small improvement.

When `step` is 16, the `andi` instruction in the loop performs a bitwise AND with immediate mask value 0xFFFF. This will emit 3 instructions. It's effectively a zero extension operation and could be reduced to 1 or 2 instructions repectively depending on whether Zbb extension is available. And there is no difference when `step` is 8 with this change.

Testing: tier1 and gtest:all are clean on Premier-P550 SBC running Ubuntu-24.04.

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Commit messages:
 - 8346475: RISC-V: Small improvement for MacroAssembler::ctzc_bit

Changes: https://git.openjdk.org/jdk/pull/22800/files
  Webrev: https://webrevs.openjdk.org/?repo=jdk&pr=22800&range=00
  Issue: https://bugs.openjdk.org/browse/JDK-8346475
  Stats: 8 lines in 2 files changed: 2 ins; 0 del; 6 mod
  Patch: https://git.openjdk.org/jdk/pull/22800.diff
  Fetch: git fetch https://git.openjdk.org/jdk.git pull/22800/head:pull/22800

PR: https://git.openjdk.org/jdk/pull/22800