RFR: 8346475: RISC-V: Small improvement for MacroAssembler::ctzc_bit [v3]

[Fei Yang]

> Hi, please review this small improvement.
> 
> When `step` is 16, the `andi` instruction in the loop performs a bitwise AND with immediate mask value 0xFFFF. This will emit 3 instructions. It's effectively a zero extension operation and could be reduced to 1 or 2 instructions repectively depending on whether Zbb extension is available. And there is no difference when `step` is 8 with this change.
> 
> Testing: tier1 and gtest:all are clean on Premier-P550 SBC running Ubuntu-24.04.

Fei Yang has updated the pull request incrementally with two additional commits since the last revision:

 - Review comments
 - Review comments

-------------

Changes:
  - all: https://git.openjdk.org/jdk/pull/22800/files
  - new: https://git.openjdk.org/jdk/pull/22800/files/f4d9b181..714f2b94

Webrevs:
 - full: https://webrevs.openjdk.org/?repo=jdk&pr=22800&range=02
 - incr: https://webrevs.openjdk.org/?repo=jdk&pr=22800&range=01-02

  Stats: 3 lines in 1 file changed: 0 ins; 2 del; 1 mod
  Patch: https://git.openjdk.org/jdk/pull/22800.diff
  Fetch: git fetch https://git.openjdk.org/jdk.git pull/22800/head:pull/22800

PR: https://git.openjdk.org/jdk/pull/22800