Integrated: 8346475: RISC-V: Small improvement for MacroAssembler::ctzc_bit

[Fei Yang]

On Wed, 18 Dec 2024 00:47:48 GMT, Fei Yang <fyang at openjdk.org> wrote:

> Hi, please review this small improvement.
> 
> When `step` is 16, the `andi` instruction in the loop performs a bitwise AND with immediate mask value 0xFFFF. This will emit 3 instructions. It's effectively a zero extension operation and could be reduced to 1 or 2 instructions repectively depending on whether Zbb extension is available. And there is no difference when `step` is 8 with this change.
> 
> Testing: tier1 and gtest:all are clean on Premier-P550 SBC running Ubuntu-24.04.

This pull request has now been integrated.

Changeset: 6b89954c
Author:    Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.org/jdk/commit/6b89954c65342bc601633d24075dab4f4b248f4b
Stats:     35 lines in 4 files changed: 13 ins; 5 del; 17 mod

8346475: RISC-V: Small improvement for MacroAssembler::ctzc_bit

Reviewed-by: mli, fjiang

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PR: https://git.openjdk.org/jdk/pull/22800