RFR: 8346478: RISC-V: Refactor add/sub assembler routines [v3]

[Fei Yang]

On Fri, 20 Dec 2024 12:38:22 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

> Hey,
> 
> As we have instructions **and** and **andi** but in asm they are called **andr** and **andi**, I suggest we apply this to add/sub also?

Hi, that's exactly what I am thinking for now :-) I guess this might help with other naming issues as well.
I don't really like other macro-assember routine names such as `MacroAssembler::ror_imm`. I think it should be something simpler like `MacroAssembler::ror`. But we need to rename the `Assembler::ror` as `Assembler::rorr` first.

BTW: We cannot use names like `and`/`xor`/`or` because they are standard C++ operators. That's why we use `andr`/`xorr`/`orr`  for RISC-V and other CPU platforms.

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PR Comment: https://git.openjdk.org/jdk/pull/22804#issuecomment-2556944440